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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad5307/ad5317/ad5327 * 2.5 v to 5.5 v, 400 a, quad voltage output 8-/10-/12-bit dacs in 16-lead tssop * protected by u.s. patent no. 5,969,657; other patents pending. features ad5307: 4 buffered 8-bit dacs in 16-lead tssop a version: 1 lsb inl, b version: 0.625 lsb inl ad5317: 4 buffered 10-bit dacs in 16-lead tssop a version: 4 lsb inl, b version: 2.5 lsb inl ad5327: 4 buffered 12-bit dacs in 16-lead tssop a version: 16 lsb inl, b version: 10 lsb inl low power operation: 400 a @ 3 v, 500 a @ 5 v 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 90 na @ 3 v, 300 na @ 5 v ( pd pin) double-buffered input logic buffered/unbuffered reference input options output range: 0 v to v ref or 0 v to 2 v ref power-on reset to 0 v simultaneous update of outputs ( ldac pin) asynchronous clear facility ( clr pin) low power, spi , qspi, microwire, and dsp compatible 3-wire serial interface sdo daisy-chaining option on-chip rail-to-rail output buffer amplifiers temperature range ?0 c to +105 c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources functional block diagram input register v out a buffer string dac a v dd gnd ad5307/ad5317/ad5327 v out b buffer string dac b v out c buffer string dac c v out d buffer string dac d gain-select logic v ref ab v ref cd sync sclk din sdo clr dcen ldac pd power-on reset power-down logic ldac dac register input register dac register input register dac register input register dac register interface logic general description the ad5307/ad5317/ad5327 are quad 8-, 10-, and 12-bit buffered voltage-output dacs in a 16-lead tssop package that operate from a single 2.5 v to 5.5 v supply, consuming 400 m a at 3 v. their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 v/ m s. the ad5307/ ad5317/ad5327 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with standard spi, qspi, microwire, and dsp interface standards. the references for the four dacs are derived from two refer- ence pins (one per dac pair). these reference inputs can be configured as buffered or unbuffered inputs. the parts incorpo- rate a power-on reset circuit, which ensures that the dac outputs power up to 0 v and remain there until a valid write to the device takes place. there is also an asynchronous active low clr pin that clears all dacs to 0 v. the outputs of all dacs may be updated simultaneously using the asynchronous ldac input. the parts contain a power-down feature that reduces the cur- rent consumption of the devices to 300 na @ 5 v (90 na @ 3 v). the parts may also be used in daisy-chaining applications using the sdo pin. all three parts are offered in the same pinout, which allows users to select the amount of resolution appropriate for their applica- tion without redesigning their circuit board. programmable attenuators industrial process control
rev. a e2e ad5307/ad5317/ad5327especifications (v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specitcations t min to t max , unless otherwise noted.) a version 2 b version 2 parameter 1 min typ max min typ max unit conditions/comments dc performance 3, 4 ad5307 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5317 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5327 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 5 60 5 60 mv v dd = 4.5 v, gain = 2; see figures 4 and 5 gain error 0.3 1.25 0.3 1.25 % of fsr v dd = 4.5 v, gain = 2; see figures 4 and 5. lower deadband 5 10 60 10 60 mv see figure 4. lower deadband exists only if offset error is negative. upper deadband 5 10 60 10 60 mv see figure 5. upper deadband exists only if v ref = v dd and offset plus gain error is positive. offset error drift 6 e12 e12 ppm of fsr/ v dd = 10% dc crosstalk 6 200 200 m vr l = 2 k w to gnd or v dd dac reference inputs 6 v ref input range 1 v dd 1v dd v buffered reference mode 0.25 v dd 0.25 v dd v unbuffered reference mode v ref input impedance (r dac ) >10 >10 m w buffered reference mode and power-down mode 74 90 74 90 k w unbuffered reference mode. 0 v to v ref output range 37 45 37 45 k w unbuffered reference mode. 0 v to 2 v ref output range reference feedthrough e90 e90 db frequency = 10 khz channel-to-channel isolation e75 e75 db frequency = 10 khz output characteristics 6 minimum output voltage 7 0.001 0.001 v this is a measure of the minimum maximum output voltage 7 v dd e 0.001 v dd e 0.001 v and maximum drive capability of the output ampliter. dc output impedance 0.5 0.5 w short circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 m s coming out of power-down mode. v dd = 5 v 55 m s coming out of power-down mode. v dd = 3 v
rev. a ad5307/ad5317/ad5327 e3e logic inputs 6 input current 1 1 m a v il , input low voltage 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v v ih , input high voltage (excluding dcen) 1.7 1.7 v v dd = 2.5 v to 5.5 v; ttl and 1.8 v cmos compatible v ih , input high voltage (dcen) 2.4 2.4 v v dd = 5 v 10% 2.1 2.1 v v dd = 3 v 10% 2.0 2.0 v v dd = 2.5 v pin capacitance 3 3 pf logic output (sdo) 6 v dd = 4.5 v to 5.5 v output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd e 1 v dd e 1 v i source = 2 ma v dd = 2.5 v to 3.6 v output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd e 0.5 v dd e 0.5 v i source = 2 ma floating state leakage current 1 1 m a dcen = gnd floating state output capacitance 3 3 pf dcen = gnd power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 8 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 500 900 500 900 m a all dacs in unbuffered mode. in buffered mode, extra current is typically x m a per dac v dd = 2.5 v to 3.6 v 400 750 400 750 m a where x = 5 m a + v ref /r dac . i dd (power-down mode) v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.3 1 0.3 1 m a v dd = 2.5 v to 3.6 v 0.09 1 0.09 1 m a notes 1 see the terminology section. 2 temperature range (a, b versions): e40
rev. a e4e ad5307/ad5317/ad5327 timing characteristics 1, 2, 3 (v dd = 2.5 v to 5.5 v; all specitcations t min to t max , unless otherwise noted.) a, b versions parameter limit at t min , t max unit conditions/comments t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 50 ns min minimum sync high time t 9 20 ns min ldac pulsewidth t 10 20 ns min sclk falling edge to ldac rising edge t 11 20 ns min clr pulsewidth t 12 0 ns min sclk falling edge to ldac falling edge t 13 4, 5 20 ns max sclk rising edge to sdo valid (v dd = 3.6 v to 5.5 v) 25 ns max sclk rising edge to sdo valid (v dd = 2.5 v to 3.5 v) t 14 5 5 ns min sclk falling edge to sync rising edge t 15 5 8 ns min sync rising edge to sclk rising edge t 16 5 0 ns min sync rising edge to ldac falling edge notes 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figures 2 and 3. 4 this is measured with the load circuit of figure 1. t 13 determines maximum sclk frequency in daisy-chain mode. 5 daisy-chain mode only. specifications subject to change without notice. ac characteristics 1 a, b versions 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5307 6 8 m s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5317 7 9 m s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5327 8 10 m s 1/4 scale to 3/4 scale change (0x400 to 0xc00) slew rate 0.7 v/ m s major-code change glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s sdo feedthrough 4 nv-s daisy-chain mode; sdo load is 10 pf digital crosstalk 0.5 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p. unbuffered mode total harmonic distortion e70 db v ref = 2.5 v 0.1 v p-p. frequency = 10 khz notes 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range (a, b versions): e40
rev. a ad5307/ad5317/ad5327 e5e sclk sync din t 2 t 3 t 5 t 6 t 4 t 1 t 14 db15 db0 db15' db0' db0 sdo input word for dac n input word for dac (n+1) undefined input word for dac n t 8 t 15 t 13 db15 t 16 t 9 ldac figure 3. daisy-chaining timing diagram i oh i ol to output pin v oh (min) c l 50pf 2ma 2ma figure 1. load circuit for digital output (sdo) timing specifications sclk sync din t 2 t 3 t 5 t 6 t 7 db15 t 1 db0 t 9 t 10 ldac 1 ldac 2 t 8 t 11 clr t 12 notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 figure 2. serial interface timing diagram
rev. a e6e ad5307/ad5317/ad5327 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5307/ad5317/ad5327 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 ja ja thermal impedance . . . . . . . . . . . . . . . . . . . 150.4
rev. a ad5307/ad5317/ad5327 e7e pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 clr ldac v dd v out a v out b v out c v ref ab v ref cd sdo sync sclk din gnd v out d pd dcen ad5307/ ad5317/ ad5327 pin function descriptions pin no. mnemonic function 1 clr active low control input that loads all zeros to all input and dac registers. therefore, the outputs also go to 0 v. 2 ldac active low control input that transfers the contents of the input registers to their respective dac registers. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. alternatively, this pin can be tied perma nently low. 3v dd power supply input. these parts can be operated from 2.5 v to 5.5 v, and the supply should be decoupled with a 10 m f capacitor in parallel with a 0.1 m f capacitor to gnd. 4v out ab uffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 5v out bb uffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 6v out cb uffered analog output voltage from dac c. the output amplifier has rail-to-rail operation. 7v ref ab reference input pin for dacs a and b. it may be configured as a buffered or an unbuffered input to each or both of the dacs, depending on the state of the buf bits in the serial input words to dacs a and b. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 8v ref cd reference input pin for dacs c and d. it may be configured as a buffered or an unbuffered input to each or both of the dacs, depending on the state of the buf bits in the serial input words to dacs c and d. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 9 dcen this pin is used to enable the daisy-chaining option. this should be tied high if the part is being used in a daisy chain. the pin should be tied low if it is being used in standalone mode. 10 pd active low control input that acts as a hardware power-down option. all dacs go into power-down mode when this pin is tied low. the dac outputs go into a high impedance state and the current con- sumption of the part drops to 300 na @ 5 v (90 na @ 3 v). 11 v out db uffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 12 gnd ground reference point for all circuitry on the part. 13 din serial data input. this device has a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. the din input buffer is powered down after each write cycle. 14 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. the sclk input buffer is powered down after each write cycle. 15 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falling edges of the following 16 clocks. if sync is taken high before the 16th falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 16 sdo serial data output. can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. the serial data is transferred on the rising edge of sclk and is valid on the falling edge of the clock.
rev. a e8e ad5307/ad5317/ad5327 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer func tion. typical inl versus code plots can be seen in tpcs 1, 2, and 3. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specited differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl versus code plots can be seen in tpcs 4, 5, and 6. offset error this is a measure of the offset error of the dac and the output ampliter. (see figures 4 and 5.) it can be negative or positive. it is expressed in mv. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/
rev. a ad5307/ad5317/ad5327 e9e gain error + offset error output voltage negative offset error dac code negative offset error amplifier footroom lower deadband codes actual ideal figure 4. transfer function with negative offset output voltage positive offset error dac code gain error + offset error actual ideal upper deadband codes full scale figure 5. transfer function with positive offset (v ref = v dd )
rev. a e10e ad5307/ad5317/ad5327etypical performance characteristics code inl error (lsb) 1.0 0.5 e1.0 050 250 100 150 200 0 e0.5 t a = 25 c v dd = 5v tpc 1. ad5307 typical inl plot code dnl error (lsb) 050 250 100 150 200 e0.1 e0.2 e0.3 0.3 0.1 0.2 0 t a = 25 c v dd = 5v tpc 4. ad5307 typical dnl plot v ref (v) error (lsb) 0.50 0.25 e0.50 01 5 234 0 e0.25 v dd = 5v t a = 25 c max inl max dnl min dnl min inl tpc 7. ad5307 inl and dnl error vs. v ref code inl error (lsb) 3 0 200 1000 400 600 800 0 e1 e2 e3 2 1 t a = 25 c v dd = 5v tpc 2. ad5317 typical inl plot code dnl error (lsb) 0.4 e0.4 600 400 800 1000 0 e0.6 0.6 0.2 e0.2 t a = 25 c v dd = 5v 200 0 tpc 5. ad5317 typical dnl plot temperature ( c) error (lsb) 0.5 0.2 e0.5 40 0 40 0 e0.2 v dd = 5v v ref = 3v max inl 80 120 e0.4 e0.3 e0.1 0.1 0.3 0.4 max dnl min inl min dnl tpc 8. ad5307 inl error and dnl error vs. temperature code inl error (lsb) 12 0 e4 e8 8 4 0 4000 1000 2000 3000 e12 t a = 25 c v dd = 5v tpc 3. ad5327 typical inl plot code dnl error (lsb) 0.5 2000 3000 4000 0 e1.0 1.0 e0.5 t a = 25 c v dd = 5v 1000 0 tpc 6. ad5327 typical dnl plot gain error temperature ( c) error (% fsr) 1.0 0.5 e1.0 40 0 40 0 e0.5 v dd = 5v v ref = 2v offset error 80 120 tpc 9. ad5307 offset error and gain error vs. temperature
rev. a ad5307/ad5317/ad5327 e11e v dd (v) error (% fsr) 0.2 e0.6 01 3 0 e0.4 46 e0.5 e0.3 e0.2 e0.1 0.1 25 offset error gain error t a = 25 c v ref = 2v tpc 10. offset error and gain error vs. v dd v dd (v) i dd ( a) 600 2.5 500 400 300 200 100 0 3.0 3.5 4.0 4.5 5.0 5.5 e40 c +25 c +105 c tpc 13. supply current vs. supply voltage v out a 5s ch1 ch2 sclk t a = 25 c v dd = 5v v ref = 5v ch1 1v, ch2 5v, time base= 1 s/div tpc 16. half-scale settling (1/4 to 3/4 scale code change) sink/source current (ma) v out (v) 5 0 01 3 4 46 1 2 3 25 5v source 3v source 5v sink 3v sink tpc 11. v out source and sink current capability v dd (v) i dd ( a) 0.5 0 0.4 0.1 0.2 0.3 2.5 3.0 4.0 4.5 5.5 3.5 5.0 e40 c +25 c +105 c tpc 14. power-down current vs. supply voltage v out a t a = 25 c v dd = 5v v ref = 2v ch1 ch2 ch1 2.00v, ch2 200mv, time base = 200 s/div v dd tpc 17. power-on reset to 0 v code i dd ( a) 600 zero scale full scale 500 400 300 200 100 0 t a = 25 c v dd = 5v v ref = 2v tpc 12. supply current vs. dac code v logic (v) i dd ( a) 300 01 400 5 500 600 700 800 23 4 t a = 25 c v dd = 5v decreasing decreasing v dd = 3v increasing increasing tpc 15. supply current vs. logic input voltage for sclk and din increasing and decreasing t a = 25 c v dd = 5v v ref = 2v ch1 ch2 ch1 500mv, ch2 5.00v, time base = 1 s/div v out a pd tpc 18. exiting power-down to midscale
rev. a e12e ad5307/ad5317/ad5327 i dd ( a) frequency 350 400 500 550 450 600 v dd = 3v v dd = 5v tpc 19. i dd histogram with v dd = 3 v and v dd = 5 v v ref (v) full-scale error (v) 0.02 e0.02 01 3 0.01 e0.01 46 0 25 v dd = 5v t a = 25 c tpc 22. full-scale error vs. v ref 1 s /div 2.48 2.49 v out (v) 2.47 2.50 tpc 20. ad5327 major-code transition glitch energy 150ns/div 1mv/div tpc 23. dac-to-dac crosstalk frequency (hz) 10 e40 10 e20 e30 0 e10 db 100 1k 10k 100k 1m 10m e50 e60 tpc 21. multiplying bandwidth (small-signal frequency response)
rev. a ad5307/ad5317/ad5327 ?3 functional description the ad5307/ad5317/ad5327 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits respectively. each contains four output buffer ampli?rs and is written to via a 3-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer am pli?rs provide rail-to-rail output swing with a slew rate of 0.7 v/ m s. dacs a and b share a common reference input, v ref ab. dacs c and d share a common reference input, v ref cd. each reference input may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from 0.25 v to v dd . the devices have a power-down mode in which all dacs may be turned off completely with a high impedance output. digital-to-analog section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer ampli?r. the voltage at the v ref pin provides the reference voltage for the corresponding dac. figure 6 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by v vd out ref n = 2 where: d = decimal equivalent of the binary code that is loaded to the dac register: 0?55 for ad5307 (8 bits) 0?023 for ad5317 (10 bits) 0?095 for ad5327 (12 bits) n = dac resolution v out a gain mode (gain = 1 or 2) v ref ab buf dac register input register resistor string output buffer amplifier reference buffer figure 6. single dac channel architecture resistor string the resistor string section is shown in figure 7. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output ampli?r. the voltage is tapped off by closing one of the switches connecting the string to the ampli?r. because it is a string of resistors, it is guaranteed monotonic. dac reference inputs there is a reference pin for each pair of dacs. the reference inputs are buffered but can also be individually configured as unbuffered. the advantage with the buffered input is the high impedance it presents to the voltage source driving it. how- ever, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 v and as high as v dd since there is no restriction due to headroom and footroom of the reference amplifier. to output amplifier r r r r r figure 7. resistor string if there is a buffered reference in the circuit (e.g., ref192), there is no need to use the on-chip buffers of the ad5307/ad5317/ ad5327. in unbuffered mode, the input impedance is still large at typically 90 k w per reference input for 0 v to v ref mode and 45 k w for 0 v to 2 v ref mode. the buffered/unbuffered option is controlled by the buf bit in the data-word. the buf bit setting applies to whichever dac is selected. output ampli?r the output buffer amplifier is capable of generating output voltages to within 1 mv of either rail. its actual range depends on the value of v ref , gain, offset error, and gain error. if a gain of 1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain = 1), the output range is 0.001 v to 2 v ref . because of clamping, however, the maximum output is limited to v dd ?0.001 v. the output amplifier is capable of driving a load of 2 k w to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in tpc 11. the slew rate is 0.7 v/ m s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 m s. power-on reset the ad5307/ad5317/ad5327 are provided with a power-on reset function so that they power up in a de?ed state. the power-on state is normal operation reference inputs unbuffered 0 v to v ref output range output voltage set to 0 v both input and dac registers are ?led with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up.
rev. a e14e ad5307/ad5317/ad5327 serial interface the ad5307/ad5317/ad5327 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with spi, qspi, microwire, and dsp interface standards. input shift register the input shift register is 16 bits wide. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. the timing diagram for this operation is shown in fig ure 2. the 16-bit word consists of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. data is loaded msb first (bit 15), and the first two bits determine whether the data is for dac a, dac b, dac c, or dac d. bits 13 and 12 control the operating mode of the dac. bit 13 is gain, which determines the output range of the part. bit 12 is buf, which controls whether the reference inputs are buffered or unbuffered. table i. address bits for the ad53x7 a1 (bit 15) a0 (bit 14) dac addressed 00 dac a 01 dac b 10 dac c 11 dac d control bits gain controls the output range of the addressed dac. 0: output range of 0 v to v ref . 1: output range of 0 v to 2 v ref . a1 buf d7 d6 d5 d4 d3 d2 d1 d0 xxxx bit 0 (lsb) bit 15 (msb) data bits gain a0 figure 8. ad5307 input shift register contents data bits a1 buf xx bit 0 (lsb) bit 15 (msb) gain a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 figure 9. ad5317 input shift register contents data bits a1 buf bit 0 (lsb) bit 15 (msb) gain a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 figure 10. ad5327 input shift register contents buf controls whether reference of the addressed dac is buffered or unbuffered. 0: unbuffered reference. 1: buffered reference. the ad5327 uses all 12 bits of dac data; the ad5317 uses 10 bits and ignores the 2 lsb. the ad5307 uses eight bits and ignores the last four bits. the data format is straight binary, with all 0s corresponding to 0 v output and all 1s corresponding to full-scale output (v ref e 1 lsb). the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can be trans ferred in to th e de v ice only while sync is low. to start the serial data transfer, sync should be taken low, observing the minimum sync to sclk falling edge setup time, t 4 . after sync goes low, serial data will be shifted into the device?s input shift register on the falling edges of sclk for 16 clock pulses. in standalone mode (dcen = 0), any data and clock pulses after the 16th falling edge of sclk will be ignored and no further serial data transfer will occur until sync is taken high and low again. sync may be taken high after the falling edge of the 16th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected dac. if sync is taken high before the 16th falling edge of sclk, the data transfer will be aborted and the dac input registers will not be updated.
rev. a ad5307/ad5317/ad5327 e15e when data has been transferred into the input register of a dac, the corresponding dac register and dac output can be updated by taking ldac low. clr is an active low, asynchro- nous clear that clears the input registers and dac registers to all 0s. low power serial interface to minimize the power consumption of the device, the interface powers up fully only when the device is being written to, i.e., on the falling edge of sync . the sclk and din input buffers are powered down on the rising edge of sync . daisy-chaining for systems that contain several dacs, or where the user w ishes to read back the dac contents for diagnostic purposes, the sdo pin may be used to daisy-chain several devices together and provide serial readback. by connecting the dcen (daisy-chain enable) pin high, the daisy-chain mode is enabled. it is tied low in the case of stand- alone mode. in daisy-chain mode, the internal gating on s clk is disabled. the sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the din input on the next dac in the chain, a multi-dac interface is constructed. sixteen clock pulses are required for each dac in the system. therefore, the total number of clock cycles must equal 16n, where n is the total number of devices in the chain. when the serial transfer to all devices is complete, sync should be taken high. this prevents any further data from being clocked into the input shift register. a continuous sclk source may be used if it can be arranged that sync is held low for the correct number of clock cycles. alternatively, a burst clock containing the exact number of clock cycles may be used and sync may be taken high some time later. when the transfer to all input registers is complete, a common ldac signal updates all dac registers and all analog outputs are updated simultaneously. double-buffered interface the ad5307/ad5317/ad5327 dacs have double-buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register and the digital code is transferred to the rel evant input register on completion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. access to the dac registers is controlled by the ldac pin. when the ldac pin is high, the dac registers are latched and the input registers may change state without affecting the contents of the dac registers. when ldac is brought low, how ever, the dac registers become transparent and the contents of the input registers are transferred to them. the double-buffered interface is useful if the user requires simu lta- neous updating of all dac outputs. the user may write to three of the input registers individually and then, by bringing ldac low when writing to the remaining dac input register, all out puts will update simultaneously. these parts contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5307/ad5317/ad5327, the part will update the dac register only if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. load dac input ( ldac ldac dac ldac daca ldac synchronous mode : in this mode, the dac registers are up dated after new data is read in on the falling edge of the 16th sclk pulse. ldac can be tied permanently low or pulsed as in figure 2. asynchronous mode : in this mode, the outputs are not up dated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the con- tents of the input register. power-down mode the ad5307/ad5317/ad5327 have low power consumption, typically dissipating 1.2 mw with a 3 v supply and 2.5 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into power- down mode, which is selected by taking the pd pin low. when the pd pin is high, all dacs work normally with a typical power consumption of 500 m a at 5 v (400 m a at 3 v). however, in power-down mode, the supply current falls to 300 na at 5 v (90 na at 3 v) when all dacs are powered down. not only does the supply current drop, but the output stage is also inter- nally switched from the output of the amplifier, making it an open circuit. this has the advantage that the output is three- state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. the output stage is illustrated in figure 11. the bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. in fact, it is pos- sible to load new data to the input registers and dac registers during power-down. the dac outputs will update as soon as pd goes high. the time to exit power-down is typically 2.5 m s for v dd = 5 v and 5 m s when v dd = 3 v. this is the time from the rising edge of pd to when the output voltage deviates from its power-down voltage. see tpc 18 for a plot. resistor string dac power-down circuitry amplifier v out figure 11. output stage during power-down
rev. a e16e ad5307/ad5317/ad5327 microprocessor interfacing adsp-2101/adsp-2103 to ad5307/ad5317/ad5327 interface figure 12 shows a serial interface between the ad5307/ad 5317/ ad5327 and the adsp-2101/adsp-2103. the adsp-2101/ adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the dsp?s serial clock and clocked into the ad5307/ad5317/ad 5327 on the falling edge of the dac?s sclk. ad5307/ ad5317/ ad5327 * sclk din sync tfs dt sclk adsp-2101/ adsp-2103 * * additional pins omitted for clarity figure 12. adsp-2101/adsp-2103 to ad5307/ ad5317/ad5327 interface 68hc11/68l11 to ad5307/ad5317/ad5327 interface figure 13 shows a serial interface between the ad5307/ad 5317/ ad5327 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5307/ad5317/ ad5327, while the mosi output drives the serial data line (din) of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be config- ured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as above, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5307/ad5317/ad5327, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac; pc7 is taken high at the end of this procedure. din sclk sync pc7 sck mosi 68hc11/68l11 * * additional pins omitted for clarity ad5307/ ad5317/ ad5327 * figure 13. 68hc11/68l11 to ad5307/ad5317/ ad5327 interface 80c51/80l51 to ad5307/ad5317/ad5327 interface figure 14 shows a serial interface between the ad5307/ad 5317/ ad5327 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5307/ad5317/ad5327, while rxd drives the serial data line of the part. the sync signal is again derived from a bit programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5307/ ad5317/ad5327, p3.3 is taken low. the 80c51/80l51 trans- mits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/ 80l51 outputs the serial data in a format that has the lsb first. the ad5307/ad5317/ad5327 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. din sclk sync p3.3 txd rxd 80c51/80l51 * * additional pins omitted for clarity ad5307/ ad5317/ ad5327 * figure 14. 80c51/80l51 to ad5307/ad5317/ad5327 interface microwire to ad5307/ad5317/ad5327 interface figure 15 shows an interface between the ad5307/ad5317/ ad5327 and any microwire compatib le device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the ad5307/ad5317/ad5327 on the rising edge of sk, which corresponds to the falling edge of the dac?s sclk. din sclk sync cs sk so microwire * * additional pins omitted for clarity ad5307/ ad5317/ ad5327 * figure 15. microwire to ad5307/ad5317/ad5327 interface
rev. a ad5307/ad5317/ad5327 e17e applications typical application circuit the ad5307/ad5317/ad5327 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 v to v dd . more typically, these devices are used with a fixed, precision reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference would be the ad589, a 1.23 v band gap reference. figure 16 shows a typical setup for the ad5307/ ad5317/ad5327 when using an external reference. 1 f v ref ab v ref cd v out v in 0.1 f 10 f sclk din sync gnd v out a v out d ad5307/ad5317/ ad5327 serial interface ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v v out c v out b v dd = 2.5v to 5.5v ext ref figure 16. ad5307/ad5317/ad5327 using a 2.5 v external reference driving v dd from the reference voltage if an output range of 0 v to v dd is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference input to v dd . as this supply may be noisy and not very accurate, the ad5307/ad5317/ad5327 may be powered from the reference voltage, for example, using a 5 v reference such as the ref195. the ref195 will output a steady supply voltage for the ad5307/ad5317/ad5327. the typical current required from the ref195 is 500 m a supply current and a 112 m a into the reference inputs (if unbuffered). this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k w load on each output) is 612 4 5 10 2 6 m avk ma + () = /. w the load regulation of the ref195 is typically 2 ppm/ma, w hich results in an error of 5.2 ppm (26 m v) for the 2.6 ma current drawn from it. this corresponds to a 0.0013 lsb error at eight bits and 0.021 lsb error at 12 bits. bipolar operation using the ad5307/ad5317/ad5327 the ad5307/ad5317/ad5327 have been designed for single- supply operation, but a bipolar output range is also possible using the circuit in figure 17. this circuit will give an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: v refin d r r r refin r r out n = () + () () ? ? ? ? ? 212 121 ? where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. with refin = 5 v, r 1 = r 2 = 10 k w : vdv out n = () 10 2 5 /e 1 f v ref ab v dd v out a 10 f 0.1 f 5v ad820/ op295 5v +5v r1 10k r2 10k sclk sync gnd serial interface v out v in gnd ref195 e5v v out b v out c v out d 6v to 16v v ref cd ad5307/ad5317/ ad5327 din figure 17. bipolar operation with the ad5307/ ad5317/ad5327
rev. a e18e ad5307/ad5317/ad5327 opto-isolated interface for process control applications the ad5307/ad5317/ad5327 have a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process control and industrial applications. due to noise, safety requirements, or distance, it may be necessary to isolate the ad5307/ad5317/ad5327 from the controller. this can easily be achieved by using opto-isolators that will provide isolation in excess of 3 kv. the actual data rate achieved may be limited by the type of optocouplers chosen. the serial loading structure of the ad5307/ad5317/ad5327 makes them ideally suited for use in opto-isolated applications. figure 18 shows an opto-isolated interface to the ad5307/ad5317/ad5327 where din, sclk, and sync are driven from optocouplers. the power supply to the part also needs to be isolated. this is done by using a trans former. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5307/ad5317/ad5327. v dd sclk 10k v ref ab din sync v dd gnd v out a 0.1 f 10 f v ref cd v out b sclk 5v regulator power v dd sync 10k v dd din 10k v out c v out d ad5307 dcen figure 18. ad5307 in an opto-isolated interface decoding multiple ad5307/ad5317/ad5327s the sync pin on the ad5307/ad5317/ad5327 can be used in applications to decode a number of dacs. in this applica tion, all the dacs in the system receive the same serial clock and serial data, but only the sync to one of the devices will be active at any one time, allowing access to four channels in this 16-channel system. the 74hc139 is used as a 2-to-4 line de coder to address any of the dacs in the system. to prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 19 shows a diagram of a typical setup for decoding multiple ad5307 devices in a system. 74hc139 v cc v dd enable coded address 1g 1a 1b dgnd 1y0 1y1 1y2 1y3 sclk din sync din sclk v out a v out b v out c v out d sync din sclk sync din sclk sync din sclk ad5307 v out a v out b v out c v out d v out a v out b v out c v out d v out a v out b v out c v out d ad5307 ad5307 ad5307 figure 19. decoding multiple ad5307 devices in a system ad5307/ad5317/ad5327 as a digitally programmable window detector a digitally programmable upper/lower limit detector using two of the dacs in the ad5307/ad5317/ad5327 is shown in figure 20. the upper and lower limits for the test are loaded to dacs a and b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led will indicate the fail condition. similarly, dacs c and d can be used for window detection on a second v in signal. ad5307/ad5317/ ad5327 v ref ab v ref cd sclk din sync v dd gnd v out a v out b 5v 0.1 f 10 f sclk din sync v ref v in 1/2 cmp04 1k fail pass/ fail 1k pass 1/6 74hc05 figure 20. window detection
rev. a ad5307/ad5317/ad5327 e19e daisy-chaining for systems that contain several dacs, or where the user w ishes to read back the dac contents for diagnostic purposes, the sdo pin may be used to daisy-chain several devices together and provide serial readback. figure 3 shows the timing diagram for daisy-chain applications. the daisy-chain mode is en abled by connecting dcen high. see figure 21. 68hc11 * miso sync din sclk mosi sck pc7 pc6 ldac sdo sync sclk ldac sdo sync sclk ldac sdo din din * additional pins omitted for clarity ad5307 * ad5307 * ad5307 * dcen dcen dcen figure 21. ad5307 in daisy-chain mode power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5307/ad5317/ad5327 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5307/ad5317/ad5327 is in a system where multiple devices require an agnd-to- dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5307/ad5317/ad5327 should have ample supply bypassing of 10 m f in parallel with 0.1 m f on the supply located as close to the package as possible, ideally right up against the device. the 10 m f capacitors are the tantalum bead type. the 0.1 m f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5307/ad5317/ad5327 sh ould use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip tech nique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
rev. a ?0 ad5307/ad5317/ad5327 table ii. overview of ad53xx serial devices no. of settling part no. resolution dacs dnl interface time ( s) package pins singles ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.5 spi 7 msop 10 ad5324 12 4 1.0 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16 visit www.analog.com/support/standard_linear/selection_guides/ad53xx.html for more information. table iii. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time ( s) additional pin functions package pins singles buf gain hben clr ad5330 8 0.25 1 6 ?? ? tssop 20 ad5331 10 0.5 1 7 ?? tssop 20 ad5340 12 1.0 1 8 ?? ? tssop 24 ad5341 12 1.0 1 8 ?? ? ? tssop 20 duals ad5332 8 0.25 2 6 ? tssop 20 ad5333 10 0.5 2 7 ?? ? tssop 24 ad5342 12 1.0 2 8 ?? ? tssop 28 ad5343 12 1.0 1 8 ?? tssop 20 quads ad5334 8 0.25 2 6 ?? tssop 24 ad5335 10 0.5 2 7 ?? tssop 24 ad5336 10 0.5 4 7 ?? tssop 28 ad5344 12 1.0 4 8 tssop 28
rev. a ad5307/ad5317/ad5327 ?1 outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab revision history location page 8/03?ata sheet changed from rev. 0 to rev. a. added a version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to tpc 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 added octals section to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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